1. Field of the Invention
The present invention relates to an improved method and apparatus for selectively charge addressing individual MNOS memory cells of an MNOS transistor array.
2. State of the Prior Art
In the prior art, conventional single gate MNOS memory cells are employed and individually read by use of a current-sense flip-flop circuit, as is typically shown in FIG. 1. The flip-flop circuit 10 is conventional and, for illustration purposes, comprises transistors 1, 3, 5 and 7. The flip-flop circuit 10 is initially set so that both sides are at substrate voltage V.sub.s by an initiate signal I.sub.s applied to transistors 3 and 5, turning them on. When the MNOS cell 2 is to be read, the transistors 3 and 5 are turned off by the initiate signal I.sub.s and the flip-flop circuit 10 enters a "race" condition to determine which side of the flip-flop circuit 10 will first provide the current sufficiently large to set the opposite side in a "1" state. A reference transistor 4, having its gate connected to a reference voltage V.sub.D, is connected to one side of the flip-flop circuit. The other side of the flip-flop circuit is connected to the MNOS memory cell while a read voltage V.sub.M is applied thereto. Thus, the memory cell current competes with the reference transistor current. A transfer signal applied to a transfer gate 6 provides access to a stage of a parallel-in shift register 15. The sensing of the MNOS cell 2 against the reference transistor 4 is performed in the source-follower mode, which is characterized by a relatively slow decision speed. The operation of the prior art circuit shown in FIG. 1 is critically dependent upon the adjustment of the "current window" which may be controlled by an adjustment of the reference signal voltage V.sub.D. Unfortunately, the required reference signal voltage may be different for each memory cell and a single reference supply is often not sufficient to similarly adjust the "current window" across a large array of memory cells.
In addition to the problems recited above, a more serious problem is encountered when high density arrays are required. In general, as the memory array size and cell density increases, the dimensions of the memory cell decreases and the drive current capacity of the memory cell becomes smaller, thereby increasing the time required to charge the capacitance C of the columns. Therefore, the prior art technique shown in FIG. 1, for reading a memory cell, has an access time to first bit which increases as the memory array size increases or the memory cell size decreases. It is seen as a near impossibility to implement the prior art memory array and read out system on a LSI chip of 16K bit or greater, since the flip-flop circuits must be placed on the pitch of the memory array.